1. Field of the Invention
The present invention generally relates to a method of making a diffused Lightly Doped Drain (LDD) semiconductor device, and, more particularly, to a LDD Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with low junction leakage.
2. Description of the Related Art
The present invention is applicable to conventional CMOS devices, and in particular to dynamic memory devices. Static memory cells store data as a stable state of a flip-flop device. The data is retained as long as dc power is supplied to the device. On the other hand, dynamic memory cells store binary data as charge on a capacitance.
The typical dynamic array, for example, a Dynamic Random Access Memory (DRAM) array, is composed of a large numbers of memory cells arranged in a matrix of rows (word lines) and columns (bit lines), each of which contains a transistor and a capacitance. Each row-column intersection stores one byte of information as a "zero" or "one". Normal leakage currents can remove stored charge in a few milliseconds (ms), so dynamic memories require periodic restoration, or refreshing, of stored charge, typically every 2-4 ms. Refreshing is performed by reading the stored data before it leaks away or every time it is read, inverting the result, and writing it back into the same location.
Retention time (RT) specifications are becoming more stringent for succeeding generations of DRAMs, that is, present DRAM applications require longer RT for low power and battery back-up applications.
As succeeding generations of DRAMs increase in memory capacity from 64 Mbit to 256 Mbit and beyond, the scaling down of the channel length and source/drain junction depth are the major challenges in improving MOSFET performance and density. Because of the limited resolution of optical lithography, realizing a sub-quarter micron gate length usually requires X-ray lithography or electron beam lithography. Both processes, however, are costly, and E-beam lithography is also time consuming.
Shallow/deep source-drain regions have been formed simultaneously through the use of a disposable nitride spacer to cream an implant screen-oxide step, as reported in C. S. Oh et al., "Simultaneous Formation of Shallow-Deep Stepped Source/Drain for Sub-Micron CMOS", 1988 Symposium on VLSI Technology, May 1988. Summarizing, the shallow junction was formed next to the polysilicon gate for short channel control, and the deeper junction was formed further away from the gate region for silicide formation.
Shallow, lightly doped drain regions are also effective in controlling so-called "hot carrier" effects, preventing carriers from gaining sufficient energy to impinge into the oxide layer.
It has been found, however, that the nitride spacer etch process is a large contributor to silicon defects and RT fails. In addition, scaling the gate oxide thickness, T.sub.ox, increases the electric field in the LDD overlap region of the device, resulting in larger Gate Induced Drain Leakage (GIDL) current for a given defect density in the overlap region.
In light of the foregoing, there exists a need for a process to scale down the channel length and source/drain junction depth while decreasing silicon crystalline defect densities in the diffusion pocket and gate overlap regions. This would allow the RT to be extended, perhaps approaching one second.